This invention relates to a logic circuit test system for testing a logic circuit by supplying test patterns to the logic circuit and by comparing response outputs from the logic circuit with expected patterns, and more particularly to a logic circuit test system capable of adjusting the internal state of a plurality of logic circuits under test to the identical initial state and of testing the plurality of logic circuits simultaneously after the adjustment.
In testing a logic circuit, test patterns and expected patterns are simultaneously generated by a pattern generator provided in the logic circuit test system. The test patterns are supplied to a logic circuit under test and the resulting outputs from the logic circuit are compared by a comparator with the expected patterns to determine whether the logic circuit works correctly or not.
FIG. 1 shows a block diagram of a logic circuit test system of this kind. A pattern generator 11 generates a test pattern D and an expected pattern E simultaneously. The test pattern D is provided to a logic circuit 13 that is to be tested (device under test. DUT) after being shaped by a formatter 12 to predetermined logic waveforms, such as return-to zero (RZ) and non-return-to zero (NRZ) signals. The expected pattern E is delayed by a delay circuit 14 for a time corresponding to the operation delay times of the logic circuit 13 and the formatter 12. The output data from the logic circuit 13 and the expected pattern from the delay circuit 14 are compared with each other and the resulting comparison signal is provided at a terminal 41 at the timing of strobe signals from a terminal 42.
Prior to supplying the test patterns to the logic circuit under test, the logic circuit under test has to be set to an initial state for applying the test patterns for the actual testing procedure beginning with the initial state. In some logic circuits, such as microprocessors or watch circuits and the like, for initialization, the internal state is incremented cyclically by a specific logic pattern inherent to the logic circuit (hereinafter referred to as the increment pattern).
By incrementing the internal state a predetermined number of times, for example 60 times, the internal state returns to the initial state. That is, with every incrementing of the internal state 60 times, as in the above example, the initial state of the logic circuit is repeatedly set.
The number of times of applying the increment pattern to the logic circuit for repeating the same internal state is inherent to the logic circuit and is known from, for example, the technical description of the logic circuit under test. However, the internal state of the logic circuit under test at the time of beginning the application of the increment pattern is not known, since the internal state at that time depends on the previous operation of the logic circuit, or on the uncertainty which ocurred when switching on the source power. Thus, in the above example of repeating the same internal state every time the increment pattern is applied 60 times, there is a possibility that the first initial state will occur for the first time on applying the increment pattern anywhere from 0 to 59 times, depending on the internal state just prior to applying the increment pattern.
For initializing and testing a logic circuit of this kind, in the logic system of FIG. 1, the pattern generator 11 repeatedly generates an increment pattern corresponding to the logic circuit 13 that is to be tested, for incrementing the internal state, and an expected pattern which indicates the initial state of the logic circuit under test. The increment pattern is provided to the logic circuit 13, and the resulting output from the logic circuit 13 is compared with the expected pattern by the comparator 15 for detecting the initial state. When the output signal from the logic circuit 13 and the expected pattern coincide with each other, a coincidence signal is generated by the comparator 15 so that a logic circuit test is started by applying test patterns for the actual test for evaluating the logic circuit 13 beginning with its initial state.
However, in the conventional logic circuit test system of FIG. 1, it is not possible to simultaneously test a plurality of logic circuits whose initial states are set by an increment pattern as mentioned above. For testing the plurality of logic circuits simultaneously in the logic test system of FIG. 1, the increment pattern and the test pattern have to be provided commonly to all the logic circuits. Since the increment pattern is provided commonly to the plurality of logic circuits, a logic circuit which has been set to the initial state earlier than another logic circuit is changed to another internal state by the increment pattern when the other logic circuit is set to the initial state.
Because of recent development in semiconductor logic circuits, logic circuit test systems for testing these logic circuits have become complicated and expensive. When using such an expensive logic test system, there is a strong demand for raising the efficiency of the test so as to reduce the cost of testing logic circuits. One of the methods for increasing the test efficiency is to test a plurality of logic circuits simultaneously with one logic test system, by applying test patterns commonly to all the logic circuits. That is, in the logic circuit test system which can test a logic circuit having up to 256 terminal pins, for example, six logic circuits, each of which as an example may have for instance 40 terminal pins in this example, can be tested in parallel at the same time. In testing a plurality of logic circuits in this manner, the test pattern has to be applied commonly to the plurality of logic circuits, because it is not feasible to generate different test patterns for each logic circuit by programming.